A 5-Gb/s Adaptive Digital CDR Circuit with SSC Capability and Enhanced High-Frequency Jitter Tolerance
Journal
IEEE Transactions on Circuits and Systems II: Express Briefs
Journal Volume
68
Journal Issue
1
Pages
161-165
Date Issued
2021
Author(s)
Chang S.-C
Abstract
A 5-Gb/s digital clock/data recovery (DCDR) circuit with spread-spectrum clocking (SSC) capability and enhanced high-frequency jitter tolerance (JTOL) is presented. To track input data with both the frequency offset and the SSC, an integral gain controller is used to adjust an integral gain of the digital loop filter. It enhances the high-frequency JTOL. This DCDR circuit is fabricated in 40nm CMOS process. Its active area is 0.022mm2 and the power consumption is 9.9mW from a 1 V supply. With a 5-Gb/s PRBS of 27-1, the measured rms jitter of the retimed data is 9.47ps. For input data with the frequency offset of ±300ppm and SSC of -5000ppm, the measured minimum high-frequency JTOL is equal to 0.55 UIpp by using the proposed integral gain controller with a bit error rate (BER) < 10{-12}. ? 2004-2012 IEEE.
Subjects
Clock and data recovery; high-frequency; jitter tolerance; phase interpolator; spread-spectrum clocking
SDGs
Other Subjects
Bit error rate; Clock and data recovery circuits (CDR circuits); Clocks; Frequency allocation; Gain control; Input output programs; Timing circuits; Digital clocks; Digital loop filters; Frequency offsets; High frequency HF; Input datas; Integral gain; Jitter tolerance; Spread spectrum clocking; Jitter
Type
journal article