An Architectural Co-Synthesis Algorithm for Energy-Aware Network-on-Chip Design
Date Issued
2005
Date
2005
Author(s)
Chang, Yen-Sheng
DOI
en-US
Abstract
Network-on-Chip has been proposed as a practical development platform for future system-on-chip products to reduce interconnection delay and to boost a good performance. In this thesis, we propose an energy-aware algorithm which simultaneously synthesizes the hardware and software architectures of a NoC-based system to meet a performance constraint and minimize total energy cost. The hardware architecture of the synthesized systems consists of an NoC platform and a set of PE (Processing Element) of multiple types; the software architecture consists of allocation of tasks to PE, the topological mapping of PEs to the NoC architecture and a static schedule for the task set. As the main contribution, we first formulate the problem of architectural co-synthesis algorithm with HW/SW co-design for a heterogeneous NoC platform and then propose an effective and efficient SA-based algorithm to solve it. With the aid of this framework, the designer can explore both hardware and software architectures simultaneously to find a system-wise energy-minimal hardware configuration along with corresponding software architecture under tight performance constraints.
Subjects
合成演算法
晶片網路
計算機結構
synthesis
architectural
NoC
Network-on-Chip
Type
thesis
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