Novel Full-Chip Gridless Routing Considering Double-Via Insertion

Date Issued

2006

Date

2006

Author(s)

Chen, Huang-Yu

Chiang, Mei-Fang

Chen, Lumdo

Han, Brian

DOI

246246/2006092815521107

URI

Abstract

Introduction Redundant-Via Aware Two-Pass Routing System Post-Layout Double-Via Insertion Algorithm Experimental Result Conclusion

Publisher

臺北市:國立臺灣大學電機工程學系

Type

report

File(s)

Name

dac06.ppt

Size

1.26 MB

Format

Microsoft Powerpoint

Checksum

(MD5):da59a4746799e976f5fc5b891da53a5c