Improved Static Learning and Its Application to PODEM
Date Issued
2015
Date
2015
Author(s)
Pan, Jiun-Han
Abstract
Reducing the automatic test pattern generation (ATPG) time is a crucial issue due to the increasing design complexity and the shrinking device feature sizes – more transistors to test and more fault models to cover. Although several learning-based ATPG acceleration techniques have been proposed, most of them are not applicable to PODEM. In this thesis we first propose an improved static learning technique called bidirec-tional implication learning. This improved learning technique can explore more necessary assignments in a circuit. Next we apply this technique to PODEM in order to avoid con-flicts; this reduces useless backtracks in sub search space that has no solution and thus speed up the test generation process. The proposed techniques are validated using ISCAS89, ITC99 benchmark circuits and 2 modern industry designs. The experiment results show that the required back-tracks are significantly reduced and the average runtime reduction is 62%.
Subjects
PODEM
implication learning
speed-up
test efficiency
Type
thesis
File(s)![Thumbnail Image]()
Loading...
Name
ntu-104-R02943087-1.pdf
Size
23.32 KB
Format
Adobe PDF
Checksum
(MD5):ab0d0d380f4ed91bdf0ee7e98a40cd13