A 20 to 24 GHz + 16.8 dBm fully integrated power amplifier using 0.18 μm CMOS process
Journal
IEEE Microwave and Wireless Components Letters
Journal Volume
19
Journal Issue
1
Pages
42-44
Date Issued
2009
Author(s)
Abstract
A 20-24 GHz, fully integrated power amplifier (PA) with on-chip input and output matching is realized in 0.18 mum standard CMOS process. By cascading two cascode stages, the PA achieves 15 dB small signal gain, 10.7% power added efficiency, 16.8 dBm output saturation power and high power density per chip area of 0.137 W/mm 2 , which is believed to be the highest power density to our knowledge. The whole chip area with pads is 0.35 mm 2 , which is the smallest one compared to all reported paper.
SDGs
Type
journal article