Design and Implementation of a Low-Jitter 6GHz Spread Spectrum Clock Generator for Serial-ATA
Date Issued
2007
Date
2007
Author(s)
Chang, Cheng-Yu
DOI
en-US
Abstract
EMI (Electro-Magnetic Interference) causes more destruction to the transmitting signal since the operating frequency is higher than before. Spread spectrum clocking (SSC) is a method that can reduce the EMI effectively. This method is more and more popular since it is easy to design and suitable for integrated IC. Serial ATA is a high speed external mass storage device having the SSC specifications as following: a triangular modulation profile with down spread, a 5000 ppm frequency deviation, a 30~33KHz modulation frequency, an EMI reduction larger than 7dB, and a 3ps RMS jitter @ 250 cycles.
Our research is stressed on low-jitter design. Due to the higher operating frequency requirement, design with low-jitter performance becomes more and more important and thus more difficult to realize. VCO phase noise dominates the jitter performance of PLLs. Therefore, we proposed a LC tank VCO with low phase noise characteristic. The simulation results show that the phase noise is -119.8dBc/Hz @1MHz offset voltage and FoM is -190.8.
In this Thesis, a spread spectrum clock generator (SSCG) modulated by a divider is presented. The PLL is fabricated in a 0.18μm CMOS process and the whole SSCG system is integrated and tested on an FPGA board. The simulation results show that all specifications of the Serial ATA have been achieved in our system and the jitter measurement shows that the RMS jitter is 0.4ps @ 250 cycles.
Subjects
展頻時脈
展頻時脈產生器
鎖相迴路
除小數式
三角積分調變器
電磁干擾
相位抖動
小數突波
壓控振盪器
SSC
SSCG
Serial ATA
PLL
Fractional-N
Δ-Σ modulator
EMI
Jitter
Fractional spurs
Voltage Controlled Oscillator
Type
thesis
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