A 6 MHz-130 MHz DLL with a fixed latency of one clock cycle delay
Resource
Custom Integrated Circuits Conference, 2002. Proceedings of the IEEE 2002
Journal
Custom Integrated Circuits Conference, 2002
Pages
-
Date Issued
2002-05
Date
2002-05
Author(s)
DOI
N/A
Abstract
In this paper, a wide range delay-locked loop (DLL) with a fixed latency of one clock cycle is proposed. Using the phase selection circuit and the start-controlled circuit enlarges the operating frequency range of this DLL and eliminates the harmonic locking problems. The operating frequency range of the DLL can be from 1/T/sub Dmin/ to 1/(N/spl times/T/sub Dmax/), where T/sub Dmin/ and T/sub Dmax/ are the minimum and maximum delay of a delay cell, respectively, and N is the number of delay cells used in the delay line theoretically. Fabricated in a 0.35 /spl mu/m 1P3M standard CMOS process, the DLL occupies an active area of 880 /spl mu/m/spl times/515 /spl mu/m and consumes a maximum power of 132 mW at 130 MHz. The measurement results show that the operating frequency range is from 6 MHz to 130 MHz and the latency is just one clock cycle. From the entire operating frequency range, the maximum r.m.s. jitter would not exceed 25 ps.
SDGs
Type
journal article
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