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College of Electrical Engineering and Computer Science / 電機資訊學院
Electrical Engineering / 電機工程學系
A 6 MHz-130 MHz DLL with a fixed latency of one clock cycle delay
Details
A 6 MHz-130 MHz DLL with a fixed latency of one clock cycle delay
Resource
Custom Integrated Circuits Conference, 2002. Proceedings of the IEEE 2002
Journal
Custom Integrated Circuits Conference, 2002
Pages
-
Date Issued
2002-05
Date
2002-05
Author(s)
Chang, Hsiang-Hui
Lin, Jyh-Woei
Liu, Shen-Iuan
DOI
10.1109/CICC.2002.1012764
DOI
N/A
URI
http://ntur.lib.ntu.edu.tw//handle/246246/2007041910021169
SDGs
[SDGs]SDG7
Type
journal article
File(s)
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Name
01012764.pdf
Size
464.38 KB
Format
Adobe PDF
Checksum
(MD5):cb07b4a5d10b49bd193ce2a9546b4f82
