A one-wire approach for skew compensating clock distribution based on bidirectional techniques
Journal
IEEE Journal of Solid-State Circuits
Journal Volume
36
Journal Issue
2
Pages
266-272
Date Issued
2001-02
Author(s)
Ching-Yuan Yang
Abstract
A clock-deskew buffer using the delay-locked loop and the bidirectional technique has been developed. It needs only one wire to synchronize the clocks for a chip-to-chip system. It has been fabricated by a 0.35-/spl mu/m n-well CMOS process. Experimental results demonstrate that it can achieve the peak-to-peak jitter smaller than 100 ps through a two-meter coaxial cable while operating at the frequency of 120 MHz. The total power dissipation of the skew buffer is 218 mW for a 3 V supply. The core chip area is 980/spl times/1700 /spl mu/m/sup 2/.
SDGs
Type
journal article