A 40.8% FBW Full D-Band Receiver Front-End Fabricated in 40 nm CMOS
Journal
2025 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2025 - Proceedings
Start Page
4
End Page
6
ISBN (of the container)
979-833150353-6
Date Issued
2026-02-03
Author(s)
Abstract
This paper presents a design for a broadband receiver front-end implemented in a 40nm CMOS process. The proposed receiver front-end includes a five-stage differential common-source Low Noise Amplifier (LNA) and a passive ring mixer with an IF buffer. Simulation results show that the system offers a 3dB bandwidth from 111 GHz to 168 GHz, reaching the highest fractional bandwidth (FBW) of 40.8%, a peak gain of 4.7 dB at 163 GHz, and a minimum noise figure (NF) of 10.1 dB at 145 GHz. This Receiver front-end demonstrates -18 dBm input 1 dB compression point (P1dB), which is suitable for frequency communication and radar systems in D-band.
Event(s)
2025 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2025
Subjects
Broadband
CMOS 40-nm
D-band
Front-end
LNA
MMIC
Receiver
Publisher
IEEE
Type
conference paper