Design of an Anticipative QoS Control Bi-directional Network-on-Chip Architecture
Date Issued
2010
Date
2010
Author(s)
Lin, Hsiao-An
Abstract
A Bidirectional channel Network-on-Chip (BiNoC) architecture with previous direction request and pipeline bypass mechanism is proposed to enhance the performance of on-chip communication while supporting prioritized traffics in the network. The Anticipative QoS controlled BiNoC not only allows each communication channel to be dynamically self-configured to transmit flits in either direction in order to better utilize on-chip hardware resources but also enhances the latency performance by using penetration and observing previous direction request. This added flexibility promises better bandwidth utilization, lower packet delivery latency, and makes high priority packet be served with better guaranteed performance. In this Thesis, an improved bi-directional on-chip router architecture supporting the hybrid bypass mechanism is presented. It is shown that the associated hardware overhead is negligible. Cycle-accurate simulations run on this AQ-BiNoC network under synthetic traffics demonstrate consistent and significant performance advantage over the conventional mesh-grid BiNoC architecture.
Subjects
Network-on-Chip
router
bi-directional channel
virtual channel
Quality-of-Service
File(s)![Thumbnail Image]()
Loading...
Name
ntu-99-R97943149-1.pdf
Size
23.32 KB
Format
Adobe PDF
Checksum
(MD5):fc4beefe9a2061166a670c72e25af014