An all-digital fast-locking programmable DLL-based clock generator
Journal
IEEE Transactions on Circuits and Systems I: Regular Papers
Journal Volume
55
Journal Issue
1
Pages
361-369
Date Issued
2008-02
Author(s)
Abstract
An all-digital fast-locking programmable DLL-based clock generator is presented. By resetting the output clock every two input clock periods, the initial minimal delay constraint in the conventional architecture is eliminated. Compared with the previous work, the short locking time is also achieved. The proposed circuit has been fabricated in 0.35-mum CMOS process and occupies the active area of 0.216 mm 2 . The clock multiplication ratio is programmed from 2 to 15. The frequency ranges of the input and output clocks are 4 ~ 200 MHz and 60 ~ 450 MHz, respectively. It dissipates less than 17 mW at all operating frequencies from a 3.3-V supply.
SDGs
Type
journal article