Shield Insertion Based Low Power Instruction Address Bus Design
Date Issued
2006
Date
2006
Author(s)
LIEN, CHUN-HSIN
DOI
en-US
Abstract
With the integrated circuits technology entering the era of deep sub-micron, the interconnections on the chip have become the performance bottleneck. The situation is especially obvious when the operating frequency is at several giga Hz because not only the parasitic capacitances result in noise but also the coupling inductances incur the signal integrity problem. In order to reduce the undesired noise and power consumption caused by parasitic elements between wires, shield insertion is a common and effective approach. In this theme, we proposed an algorithm to decide the shield insertion locations under the consideration of both capacitive and inductive coupling impacts. It partitions the whole instruction address bus into some regions according to the coupling effects between every two adjacent signal wires and finds the best shielding location based on HSPICE simulation results. Experimental results show that our method can reduce the power consumption and delay up to 1.6 times the achievements of SSIA. In the case of four shields, there is a 12.83% reduction on power consumption as well as a 1.76% reduction on delay compared to the case without any shield.
Subjects
屏蔽線插入法
功耗
雜訊
耦合效應
Shield insertion
power consumption
noise
coupling effect
HSPICE
Type
thesis
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