Generic RAM-based architecture for two-dimensional discrete wavelet transform with line-based method
Resource
Circuits and Systems, 2002. APCCAS '02. 2002 Asia-Pacific Conference on
Journal
IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS
Journal Volume
1
Pages
363 - 366
Date Issued
2002-10
Date
2002-10
Author(s)
DOI
N/A
Abstract
In this paper, by using line-based methods, a generic RAM-based architecture is proposed to construct the corresponding two-dimensional architectures efficiently for any given hardware architecture of one-dimensional wavelet filters, including conventional convolution-based and advanced lifting-based architectures. The categories of line buffer and the strategy to optimize the size of internal memory are also described. For multi-level two-dimensional discrete wavelet transforms, the recursive pyramid algorithm is adopted to turn our proposed architecture into another efficient architecture. According to the comparison results, the proposed architecture outperforms previous arts in the aspects of memory size, control complexity, and flexibility. © 2002 IEEE.
Event(s)
Asia-Pacific Conference on Circuits and Systems, APCCAS 2002
Subjects
Arithmetic; Chaos; Computer architecture; Costs; Digital signal processing; Discrete wavelet transforms; Filters; Hardware; Image coding; Random access memory
SDGs
Other Subjects
Chaos theory; Computer architecture; Computer hardware; Costs; Digital arithmetic; Digital signal processing; Filters (for fluids); Hardware; Image coding; Memory architecture; One dimensional; Random access storage; Signal processing; Wavelet transforms; Efficient architecture; Hardware architecture; Lifting-based architectures; Proposed architectures; RAM-based architectures; Random access memory; Recursive pyramid algorithms; Two-dimensional discrete wavelet transform; Discrete wavelet transforms
Type
journal article
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