A Time-to-Digital Converter for ADC Jitter Error Cancellation

The requirement of sampling clock jitter becomes rigorous in the high-speed and high-precision analog-to-digital date conversion, usually around few pico-seconds, which is unreachable for the on-chip clock generation. A method is proposed to cancel the jitter-induced errors in ADC. One of the key parameters needed here is the derivative of each sampled points. The derivative calculated from the algorithm is distorted by a sinc function as the signal frequency gets higher. A look-up table method is applied to compensate the distortion factor which makes the system to operate well near Nyquist rate. In this architecture, a time-to-digital converter (TDC) is desired to adopt the jitter cancellation algorithm in the digital domain. Besides, this TDC need to be wide dynamic range and high precision in order to cover the peak-to-peak jitter variation while maintain the accuracy. In this thesis, an MDLL-based TDC with local passive interpolation which has 10ps resolution and 5.12ns dynamic range is designed. Fabricated in a 90-nm CMOS technology, the TDC consumes 6.0mW from a 1-V power supply while the active area is only 0.017mm2.