Modeling of Jitter in Bang-Bang Clock and Data Recovery Circuits
Journal
Custom Integrated Circuits Conference
Pages
711-714
Date Issued
2003-09
Author(s)
Abstract
This paper presents an approach to analyzing bang-bang CDR loops, predicting performance aspects such as jitter transfer, jitter tolerance, jitter generation, and the bit error rate. A 1-Gb/s CDR circuit realized in 0.35-/spl mu/m CMOS technology validates the theoretical results.
SDGs
Type
conference paper