Design and Implementation of 3.125Gb/s Clock and Data Recovery Circuit Using Delay-Chain Frequency Detector
Date Issued
2007
Date
2007
Author(s)
Liu, Yen-Ting
DOI
en-US
Abstract
A clock and data recovery circuit plays an important role in wireline communication systems. It serves to recover the data with jitters and noises passed through long-distance transmission. The implementation is usually achieved by a phase-locked loop (PLL), and there are many choices for the implementation architectures. This work is divided into two parts: a half-rate CDR and a quarter-rate CDR with the delay-chain frequency detector will be reported.
A 3.125Gb/s half-rate clock and data recovery circuit is implemented first. A source follower is utilized to increase the linear tuning range of the ring oscillator. Half-rate digital quadricorrelator frequency detector (DQFD) is used to avoid the frequency drift due to the active charge pump when loop is locked. The measured power consumption is 108.4mW under a 1.8V supply voltage. The measured clock peak-peak jitter and rms jitter under 231-1 PRBS are 55.6ps and 6.61ps, respectively.
In the second part, the CDR is changed into the 1/4-rate architecture. Two clocks with two bit times difference are applied to the delay-chain frequency detector to choose the operating band of the VCO. After completing the operation of frequency selection, digital control circuits will turn off the core of the frequency detector. The measured power consumption is 103.7mW under a 1.8-V supply voltage. The measured clock peak-peak jitter and rms jitter with 2.4883Gb/s 27-1 PRBS are 31.1ps and 5.06ps, respectively.
Subjects
時脈資料回復電路
clock and data recovery circuit
Type
thesis
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