Design of a Transceiver Architecture and Performance Analysis for 10GBASE-T Ethernet System
Date Issued
2007
Date
2007
Author(s)
Tu, Yen-Ting
DOI
en-US
Abstract
In this thesis, the issues about cost down and performance improvement for 10GBASE-T Ethernet transceiver are emphasized. Three transceiver architectures are presented, including conventional transceiver architecture, transceiver architecture design based on multi-input multi-output decision feedback equalizer (MIMO-DFE)/multi-input multi-output Tomlinson-Harashima precoding (MIMO-THP) and transceiver architecture design based on channel shortening technique. Joint adaptive channel equalization and interference cancellation with proposed training methods are used to improve decision point SNR (dpSNR). Furthermore, two different architectures are presented for canceling FEXT interference at the transmitter and receiver sides during data mode, respectively. Moreover, automatic gain control (AGC) design and the resolutions of digital-to-analog converter (DAC)/analog-to-digital converter (ADC) are taken into consideration to make the whole investigation more complete. Evaluation of required phase resolution for the multi-phase clock, which will be adopted in the timing recovery mechanism, is also discussed.
The digital and analog circuits under high speed data transmission are very critical for 10GBASE-T Ethernet system, so the complexity and implementation issues are also considered specifically.
Subjects
百億位元乙太網路
收發機
等化
預編碼
串音干擾
自動增益控制
時脈回復
10GBASE-T (IEEE 802.3an) Ethernet System
Transceiver
Equalization
Precoding
Crosstalk
Automatic Gain Control
Clock Data Recovery
Type
thesis
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