Toward Suppression of Bias Instability in Monolayer WSe2 Top-Gate pFETs
Journal
IEEE Transactions on Electron Devices
Journal Volume
73
Journal Issue
8
Start Page
4531
End Page
4536
ISSN
0018-9383
1557-9646
Date Issued
2026-08-01
Author(s)
Hsu, Yu-Wei
Hsu, Chen-Hsun
Huang, Ching-Shuan
Chiang, Nien-En
Liu, Yun-Cheng
Wei, Ting-Hua
Lee, Sin-Yue
Yeh, Chris
Ni, I-Chih
Chiang, Hung-Li
Lee, Tsung-En
Abstract
This work presents the first systematic investigation of the bias instability of monolayer (1L) WSe2 top-gate p-type field-effect transistors (pFETs). A multilayer gate-stack is proposed to address the unique reliability challenges of 2D semiconductors, leveraging their van der Waals (vdW) interface for low interface trap density (Dit) and improved bias stability. The proposed stack integrates a 1 nm post-oxidized physical vapor deposition (PVD) AlOx interfacial layer (IL) to enhance hole density and suppress hydroxyl-related defects, a two-step atomic layer deposition (ALD) temperature for Hf/Zr-based higher-κ dielectrics to balance dielectric strength and channel degradation, and post-metallization annealing (PMA) for passivation of vacancy and hydrogen-related traps. With an equivalent oxide thickness (EOT) scaled to 0.8 nm, the fabricated long-channel devices achieve near-ideal subthreshold swing (S.S.) (S.S.≈ 65 mV/dec) and negligible hysteresis at room temperature. The extrapolated lifetime projection indicates excellent bias stability, with the threshold voltage shift (Δ VT) remaining below 90 mV under negative bias stress (NBS) and below 70 mV under positive bias stress (PBS) after ten years of operation at an effective stress field |Eox|=5 MV/cm. These results establish a scalable and thermally compatible gate dielectric integration for low-power 2D CMOS logic applications.
Subjects
2D material
bias stress stability
equivalent oxide thickness (EOT)
monolayer tungsten diselenide
reliability
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Type
journal article