Energy-effective design & implementation of an embedded VLIW DSP
Journal
2008 International SoC Design Conference, ISOCC 2008
Journal Volume
1
Date Issued
2008
Author(s)
Hsieh, T.-W.
Hsiao, P.-C.
Liao, C.-Y.
Hsieh, H.-C.
Lin, H.-L.
Lin, T.-J.
Chu, Y.-H.
Abstract
This paper describes the power/energy optimizations of an embedded VLIW digital signal processor (DSP) - PACDSP from the Industrial Technology Research Institute (ITRI). First, a configurable cache/scratchpad memory subsystem has been implemented, which saves the energy for tag matching in deeply embedded applications. An energy-effective cell-based design has been produced by analyzing the relationships between the energy efficiency and the synthesis constraints. Finally, dynamic voltage & frequency scaling (DVFS) and power gating have been applied to reduce both switching and leakage power dissipations with a novel Common Power Format (CPF) flow. The test-chip will be fabricated in the TSMC 90nm CMOS technology, of which the estimated power dissipations are 156.62mW for 350MHz @1V and 46.60mW for 230MHz @0.7V respectively.
SDGs
Type
conference paper