Design of High Performance Asynchronous Pipeline Circuits
Date Issued
2005
Date
2005
Author(s)
Shu, Ying-Haw
DOI
en-US
Abstract
The conventional approach of double-edge-triggered flip-flops is to have two similar edge-triggered latches. And the achieved faster speed is at the cost of double chip area and complex logic structure. By contrast, the XNOR based approaches is difficult to reach the speed demand due to the delay of the XNOR based clock generator. This paper proposes a new designed double-edge-triggered flip-flop based on an alternative XNOR gate. By utilizing the sensitivity to the driving capacity of the previous stage, we use this simplified XNOR gate as a pulse-generator. A modified transparent latch following the pulse-generator acts as an XNOR-based DET-FF, which accomplishes the almost same speed and less power dissipation as compared with two conventional DET-FFs under HSPICE simulation. We also implemented the XNOR-based DET-FF in a two-phase-pipeline system, and the HSPICE simulation in the TSMC 0.25um CMOS process shows our proposed DET-FF is much faster than those two conventional DET-FFs.
Asynchronous modules operating under two-phase micro-pipeline methodology are faster than those in common four-phase control schemes because the double-edge-triggered flip-flops in the two-phase control systems capture data twice within each clock cycle. But the conventional systems with multi-port modules normally suffer from long signal paths on stacked C-elements. NOR-based control schemes provide an alternative solution to problems such as propagation delay. This paper presents two modified designs from the common two-phase and alternative NOR-based four-phase pipeline system. The HSPICE performs the evaluation based on TSMC 0.25um fast-mode CMOS model, and HSPICE simulation results show that the two-phase pipelined system is still a reliable solution with a limited number of inputs even when the theoretically lower control overhead is disregarded. A power reduction of over 27% and a propagation improvement of more than 11% are achieved by replacing some decision circuits with modified C-elements.
Subjects
雙邊緣觸發
雙相
管線
互斥非或閘
標示訊號
多重輸出入埠
非同步
double-edge-triggered
two-phase
pipeline
XNOR
Interlocked Pipelined CMOS
Symmetric C-element
Strobe
Multi-port
Asynchronous
Type
thesis