A high-speed 6b Dynamic Folding Flash A/D Converter
Date Issued
2010
Date
2010
Author(s)
Chen, Hong-Lin
Abstract
Communication in the unlicensed frequency band around 60GHz requires a very fast ADC with low resolution (4-7 bits). Flash ADC offers the highest sampling rate, which is adapted in these high speed applications such as radio astronomy, optical communication, magnetic and optical read channels, and ultra-wideband wireless receivers. In this paper, we propose a high-speed Dynamic Folding Flash A/D Converter. Use of folding the traditional flash analog to digital converter comparator required substantially reduce the number, it can reduce the power, dynamic power consumption and does not need calibration type analog to digital converter. To alleviate random offset caused by process variation, resistive averaging technique is adopted.
This ADC is demonstrated in a standard 90-nm CMOS process. According to the measurement results, the prototype ADC exhibits a DNL of -0.6/+0.8LSB and an INL of -0.6/+0.8LSB at the sampling rate of 1GS/s. With 9.99MHz input frequency, the SNDR and SFDR achieve 33.74dB and 49.93dB at 80MS/s. The SNDR and SFDR are 30.07dB and 37.19dB at 1GS/s in 466.544MHz input frequency. The power consumption is 25mW at 1.2V supply. The active area is 0.07mm^2and whole chip with pads occupies 0.46mm^2.
Subjects
Analog-to-digital conversion
averaging network
folding
flash
Type
thesis
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