Dynamically Reconfigurable Hardware Library based of FPGA
Date Issued
2005
Date
2005
Author(s)
Ho, Chien-Wei
DOI
en-US
Abstract
Nowadays when we want to do a design, we need to software-hardware partition first. It is because that we want to put some heavy loading parts of the design into hardware. That would improve the performance of the whole design. Generally if we can put as many functions into hardware as we can, we will get much performance improvement. So, besides the software-hardware partitioning consideration, we need to have a rapidly method to let the Compute Intensive Part (CIP) run in hardware. We propose a Dynamically Reconfigurable Hardware Library (DRHL) method. When we put the CIP into DRHL, we can change to use software Intellectual Property (IP) or hardware IP smoothly. So, we can easily test if our software IP and hardware IP have the same functionality. We also can enhance computation power in System-On-Chip (SOC) with FPGA blocks. Our method provides to reach a better trade-off among flexibility performance and power.
Subjects
現場可重定址陣列
系統晶片
矽智財
FPGA
SOC
IP
Type
thesis
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