A new switching scheme for parabolic error compensation in 10 bit CMOS current steering digital to analog converter
Date Issued
2006
Date
2006
Author(s)
Chung, Cheng-Feng
DOI
zh-TW
Abstract
This thesis proposes a 10 bit 250MHz current steering DAC with a doubly segmented current steering architecture that consists of two parts: upper 5 bit MSBs and intermediate 2 bit MSBs. The other 3 bit LSBs are binary weighted current source. This design not only keeps the advantages of current steering architecture, but also consumes lower power. Two types of DACs are implemented. One is implemented by a two-dimension switching scheme, another one is implemented by the proposed switching scheme. The new switching scheme divides the MSB current source into eight parts to compensate parabolic error and also use tree structure to optimize.
This DAC is to be implemented with a UMC 0.18 µm 1P6M mixed signal CMOS process. The DNL and INL are 0.2 and 0.7 LSB, respectively. The SFDR is 64dB when the update rate is 200MHz and the input frequency is 1MHz. The power consumption is 20 mW, and it operates from 1.8V. The active area is 0.72x0.68mm2.
Subjects
數位類比轉換器
電流切換式
十位元
dac
current steering
10 bit
Type
thesis
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