A 0.02-mm2 9-bit 50-MS/s Cyclic ADC in a 90-nm Digital CMOS Technology
Resource
IEEE Journal of Solid-State Circuits, 45(3), 610-619
Journal
IEEE Journal of Solid-State Circuits
Journal Volume
45
Journal Issue
3
Pages
610-619
Date Issued
2010-03
Author(s)
Yen-Chuan Huang
Abstract
A 9-bit cyclic ADC employs a track-and-evaluation technique for enhancing the speed of residue evaluation. The proposed multiply-by-two circuit has a shorter evaluation time than the conventional design due to the application of a partial positive feedback topology. The residue evaluation and sampling phases are merged to reduce the conversion latency. Hence, only four clock cycles are required to perform the 9-bit conversion. The proposed 0.02-mm 2 ADC has been fabricated in 90-nm digital CMOS technology. It operates at 50 MS/s and achieves an SNDR of 50.5 dB with a power consumption of 6.9 mW from a 1.0-V supply.
SDGs
Type
journal article