A 24 - 16 V to 0.8 - 1.2 V Merged 4-Stage Hybrid-Sc-SL Converter with 96.5% Peak Efficiency and larger than 50% iL reduction
Journal
2025 IEEE Applied Power Electronics Conference and Exposition (APEC)
Start Page
2725-2729
Date Issued
2025-03-16
Author(s)
Abstract
This paper introduces a merged 4-stage hybrid switched-capacitor-switched-inductor converter for 24 – 16 V AI-notebook applications. The topology is based on a cascaded switched-capacitor and switched-inductor step-down converter with merged switching and energy transfer. This design ensures that the front-end switched-capacitor stage achieves complete soft-charging and automatic balance, enabling the use of mixed voltage domain power switch devices to optimize on-chip area and efficiency. Additionally, the converter achieves a greater than 50% reduction in inductor current, significantly reducing the need for bulky low DCR inductors. Implemented in a 180 nm BCD process, the proposed converter achieves a peak efficiency of 96% for 24 V to 1 V conversion and 95.52% efficiency for 24 V to 0.8V conversion. Furthermore, a peak-VIC-control with adaptive slope compensation is employed, resulting in an undershoot/overshoot of 56 mV/58 mV for a 2 A/100 ns load step-up/-down.
SDGs
Publisher
IEEE
Type
conference paper