Multi-mode embedded compression codec engine for power-aware video coding system
Resource
Signal Processing Systems Design and Implementation, 2005. IEEE Workshop on
Journal
IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
Journal Volume
2005
Pages
532-537
Date Issued
2005
Author(s)
Abstract
In a typical multi-chip handheld system for multimedia applications, external access, which is usually dominated by block-based video content, induces more than half of total system power. Embedded compression (EC) effectively reduces external access caused by video content by reducing the data size. In this paper, an algorithm and a hardware architecture of a new type EC codec engine with multiple modes are presented. Lossless mode, and lossy modes with rate control modes and quality control modes are all supported by single algorithm. The proposed four-tree pipelining scheme can reduce 83% latency and 67% buffer size between transform and entropy coding. The proposed EC codec engine can save 50%, 61%, and 77% external access at lossless mode, half-size mode, and quarter-size mode and can be used in various system power conditions. With Artisan 0.18 μm cell library, the proposed EC codec engine can encode or decode at VGA@30fps with area and power consumption of 293,605 μm 2 and 3.36 mW. © 2005 IEEE.
Event(s)
SiPS 2005: IEEE Workshop on Signal Processing Systems - Design and Implementation
SDGs
Other Subjects
Algorithms; Data compression; Embedded systems; Hand held computers; Multimedia systems; Search engines; Codec engines; Embedded compression; Entropy coding; Hardware architecture; Image coding
Type
conference paper
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