A 0.31-pJ/bit 20-Gb/s DFE with 1 Discrete Tap and 2 IIR Filters Feedback in 40-nm-LP CMOS
Journal
IEEE Transactions on Circuits and Systems II: Express Briefs
Journal Volume
64
Journal Issue
11
Pages
1282-1286
Date Issued
2017
Author(s)
Abstract
This brief presents a low-power 20-Gb/s decision feedback equalizer (DFE) with one discrete tap and two infinite impulse response (IIR) filters feedback. The advantage of the IIR-DFE lies in both great energy and area efficiency for large channel attenuations. To further enhance the power efficiency of the IIR-DFE, the charge-steering logic (CSL) is utilized in this brief. Besides, the quarter-rate topology is adopted to alleviate the race condition of the CSL-based DFE. Fabricated in a 40-nm-LP CMOS process, the DFE core circuits only consumes 6.2 mW from the 1-V supply. Moreover, the core entirely occupies an area of 5700 mu2. Measured with PRBS7, the bit error rates are all less than 10-12 for channel loss from -7.98 to -18.3 dB. Finally, the power efficiency of this IIR-DFE is 0.31 pJ/bit. © 2004-2012 IEEE.
Subjects
Charge-steering logic (CSL); decision feedback equalizer (DFE); infinite impulse response (IIR)
SDGs
Other Subjects
CMOS integrated circuits; Computer circuits; Decision feedback equalizers; Feedback; Impulse response; Area efficiency; Channel attenuation; Channel loss; Charge-steering logic (CSL); CMOS processs; Core circuit; Infinite impulse response; Power efficiency; IIR filters
Type
journal article