Design and Implementation of a Sigma-Delta Modulated Fractional-N Frequency Synthesizer
Date Issued
2005
Date
2005
Author(s)
Lin, Chia-Ching
DOI
en-US
Abstract
Nowadays, local oscillator is an essential component of the RF front-end. And the design for a frequency synthesizer with agile settling speed, low phase noise and high frequency resolution has become a challenge. The thesis discusses the influence of the MASH Sigma-Delta Modulator (SDM) to the synthesizer output phase noise. The integrated fractional-N frequency synthesizer is implemented with MASH 1-1-1 SDM. On one hand, better fractional and reference spurious suppression is achieved by randomizing the modulus of frequency dividers; on the other hand, the spurious noise is push to higher frequency and will be further filtered out by the PLL. The frequency synthesizer is operated over 4GHz. The simulated phase noise is -115dBc/Hz at 1MHz offset, and the settling time is less than 30μs at 600MHz frequency jumping.
Subjects
頻率合成器
三角積分調變
frequency synthesizer
delta-sigma modulate
fractional-n
Type
thesis
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