A TSV-Based with Multi-Layer Transmission for Low Power Strategy 3D SRAM Design
Date Issued
2014
Date
2014
Author(s)
Lai, Yi-Chi
Abstract
It’s difficult to keep following the Moore’s Law due to the larger effect of the wire resistance, wire capacitance and leakage current. According to the ITRS More-than-Moore Roadmap, the new type of technology should be developed such like FinFET, Carbon tube of 3D-IC. We choose 3D-IC to solve the mentioned problem. The TSV technology for vertical transmission is introduced to the 3D-IC process, and become a popular solution to the 3D-IC stacking issue. In the thesis, we proposed a TSV-based multi-layer transmission with free-pre-charge operation scheme. 3D-SRAM is constructed with multi-layer whole memory array and TSV for stacking. This design follows the single master scheme to control the master layer and slave layer transmission. The traditional transmission such like single-ended would cost a lot of power due to rail-to-rail transmission, especially in the wild I/O situation. Although the differential transmission creates a small swing voltage to reduce the power consumption in TSV, the pre-charge cycle in every read operation would cost tremendous power, too. Our scheme provides a free-pre-charge architecture with charge recycle and tracking systems. The proposed 64kb 3D-SRAM was fabricated in TSMC 90nm mix-signal process with 2, 4, 8, 16 layers modeling ability. The proposed design 30% power reduction, compare to single-ended transfer scheme.
Subjects
3DSRAM
TSV
Type
thesis