FinFET-based dynamic power management of on-chip interconnection networks through adaptive back-gate biasing
Part Of
Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
Start Page
350
End Page
357
ISBN (of the container)
978-142445028-2
Date Issued
2009-10
Author(s)
Niraj K. Jha
Abstract
On-chip interconnection networks are fast becoming significant power-consumers in high-performance chip multiprocessors (CMPs). Increased power consumption leads to more heat, adversely degrades system reliability, and may increase the cost of cooling IC packages. This situation becomes even worse as bulk CMOS scales further into the nanometer regime because of excessive leakage power due to short-channel effects. In this paper, we explore the use of FinFETs, which are promising substitutes for bulk CMOS at the 32 nm node and beyond, to design on-chip network routers. We present a detailed design of a variable pipeline stage router (VPSR) targeted at FinFET technology. We employ a dynamic power management scheme, which we call adaptive back-gate biasing (ABGB), for FinFET implementations. We evaluate VPSR and ABGB on a simulation platform specifically designed for power and performance simulations for FinFET-based interconnection networks. The results show that VPSR is able to successfully adapt its power consumption to incoming traffic, with a resultant 20% reduction in power at almost no impact on latency.
Event(s)
2009 IEEE International Conference on Computer Design, ICCD
SDGs
Publisher
IEEE
Type
conference paper