https://scholars.lib.ntu.edu.tw/handle/123456789/115025
標題: | 熱點快取記憶體:利用時間,空間地域性以減少指令快取記憶體耗電 HotSpot Cache: Joint Temporal and Spatial Locality Exploitation for I-Cache Energy Reduction |
作者: | 李健豪 Lee, Chien-Hao |
關鍵字: | 嵌內式系統;省電設計;指令快取記憶體;Instruction Cache;Low Power Design;Embedded Systems | 公開日期: | 2004 | 摘要: | 耗電量對嵌入式系統是一個很重要的設計上的考量。相關研究指出指令快取記憶體佔了整個晶片上很大部份的耗電。因此,有很多研究提出,加一個相對於一般指令快取而言非常小的快取記憶體 - 第零級快取憶體,以達省電效果。因為小的快取記憶體有比較小的電容量,而記憶體耗電和電容量成正比。在這篇論文當中,我提出一個新的指令快取記憶體的架構,熱點快取記憶體,它可以達到顯著的省電效果而且只有很少效能上的損失。熱點快取記憶體,能夠動態的偵測出常常執行的指令,然後把它們放到第零級的指令快取記憶體,其他的相對比較不常執行的指令放到第一級的指令快取記憶體。中間透過一個動態決定的機制,來決定指令要從那一個快取記憶體讀出來。實驗模擬的結果顯示,對於測試的幾組多媒體程式而言,熱點快取記憶體可以減少平均52%的指令快取記憶體耗電,而無顯著之效能減損。 Power consumption is an important design issue of current embedded systems. It has been shown that the instruction cache accounts for a significant portion of the power dissipation of the whole chip. Several studies propose to add a cache (L0 cache) that is very small relative to the conventional L1 cache on chip for power optimization since a smaller cache has lower load capacitance. However, energy savings often come at the cost of performance degradation. In this thesis, I propose a novel instruction cache architecture, the HotSpot cache, that achieves energy savings without sacrificing performance. The HotSpot cache identifies frequently accessed instructions dynamically and stores them in the L0 cache. Other instructions are placed only in the L1 cache. A steering mechanism is employed to direct an instruction to its allocated cache in the instruction fetch stage. The simulation results show that the HotSpot cache can achieve 52% instruction cache energy reduction on the average for a set of multimedia applications without performance degradation. |
URI: | http://ntur.lib.ntu.edu.tw//handle/246246/53688 | 其他識別: | en-US |
顯示於: | 資訊工程學系 |
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