https://scholars.lib.ntu.edu.tw/handle/123456789/115609
標題: | 以分割式快取記憶體降低碰撞失敗 Reducing Conflict Misses on Partition Cache |
作者: | 林秀萍 Lin, Hsiu-Ping |
關鍵字: | 快取記憶體;碰撞失敗;conflict misses;cache;cache misses | 公開日期: | 2004 | 摘要: | 從模擬的結果中,我們觀察到碰撞失敗 (conflict misses)佔快取記憶體失敗 (cache misses)的比例相當高。一般而言,在直接映射快取記憶體 (direct-mapped caches)中,碰撞失敗的比例大約佔30%至99%,而且大部分遠高於下限值。在兩路分組聯想式映射快取記憶體 (2-way set-associated caches)中,碰撞失敗的比例約佔20%至95%,大部份都接近下限值。因此,我們提出一個新的架構”分割式快取記憶體 (partition cache)”,應用在傳統直接映射和兩路分組聯想式映射快取記憶體上,分別稱為分割式直接映射快取記憶體 (partition direct-mapped caches)和分割式兩路分組聯想式映射快取記憶體 (partition 2-way set-associated caches)。相較於一般的快取記憶體架構,兩者都可以有效地減少碰撞失敗,平均減少碰撞失敗 (average reduction of conflict misses)的比例大約10%至98%。再者,這種新架構只須少量的硬體與執行時間需求,所以能有效率地減少碰撞失敗,進而有充分的效能提昇 (performance improvement)。根據模擬的結果,一般而言,效能提昇約10%到95%,而且在指令快取記憶體 (instruction caches)中效能提昇特別明顯。一般而言,分割式直接映射快取記憶體的效能提昇比分割式兩路分組聯想式映射快取記憶體要來的好。 此外,由於每次存取分割式快取記憶體的必v消耗只與分割快取記憶體的大小有關,所以我們提出的新架構在必v消耗上比一般的快取記憶體架構低。 We observe that the average percentage of conflict misses to all cache misses is quite high from the simulation results. In general, the average percentage of conflict misses is roughly 30%-99% in direct-mapped caches and most of them are much higher than low bound. In 2-way set-associated caches, the average percentage of conflict misses is roughly 20%-95% while most of them are near to low bound. As a result, we propose a new schema “partition cache” applied to traditional direct-mapped and 2-way set-associated caches, and we call them “partition direct-mapped caches” and “partition 2-way set-associated caches”, respectively. They can reduce conflict misses efficiently compared with conventional cache architecture. The average reduction of conflict misses is 10%-98% generally. Furthermore, with slight hardware and execution time overheads, our new schema also improves performance significantly, which is resulted from reducing conflict misses efficiently. From the simulation results, the performance improvement is 10%-95% generally, and the performance improvement is especially obvious in instruction caches. In general, the performance improvement of partition direct-mapped caches is better than that of partition 2-way set-associated caches. In addition, our schema is lower power consumption compared with conventional cache architecture. This is because the power consumption per access of the partition cache is only dependent on partition size. |
URI: | http://ntur.lib.ntu.edu.tw//handle/246246/53721 | 其他識別: | en-US |
顯示於: | 資訊工程學系 |
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ntu-93-R91922058-1.pdf | 23.31 kB | Adobe PDF | 檢視/開啟 |
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