On-Chip Bus Architecture Synthesis for SoC Design

On SoC platforms, subsystems are connected by buses on a single chip. Unlike traditional bus architecture on PCB, the bus architecture on SoC has dramatic performance effect and cost concerns. In addition, the bus architecture can now be customized for each custom SoC design, It is required for an effective and efficient bus architecture methodology. In this thesis, we proposed an iteratively heuristic approach to minimize the number of buses being used in an SoC and the location of local memory and shared. The approach gives and fast performance estimation and construct the low-cost on-chip bus architecture. The capability of the proposed approach is evaluated by extensive simulations, for which we have encouraging results.