https://scholars.lib.ntu.edu.tw/handle/123456789/116476
Title: | 硬體矽智財在系統晶片上的介面設計方法及合成 Hardware IP interface design and synthesis for System-on-a-Chip |
Authors: | 李清新 Lee, Ching-Hsin |
Keywords: | 匯流排;介面;數位矽智財;系統單晶片;bus;interface;Digital IP;IP;SoC | Issue Date: | 2006 | Abstract: | Hardware interface design is an elaborative step during intellectual property IP integration. Efficient System-on-a-Chip SoC design depends heavily on IP reuse and high level synthesis. As components of these two methods often have different communication interfaces with bus system, the design of their hardware interface is very time consuming. In this thesis, we propose a hardware interface design architecture which addresses portability, performance and verification. Our hardware interface architecture makes it possible to use data path direct-connection to increase performance. A detection technique is also presented to find out where the bottle neck of the data path is. An experimental result shows that data path direct-connection with bottleneck detection leads to up to 50% improvements in cycle counts. Our architecture also makes it possible to synthesize the hardware interface automatically. An automatic hardware interface synthesis tool is presented. |
URI: | http://ntur.lib.ntu.edu.tw//handle/246246/53904 | Other Identifiers: | en-US |
Appears in Collections: | 資訊工程學系 |
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ntu-95-R93922088-1.pdf | 23.31 kB | Adobe PDF | View/Open |
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