https://scholars.lib.ntu.edu.tw/handle/123456789/118492
標題: | Flow Time Minimization under Energy Constraints | 作者: | Chen, Jian-Jia Iwama, Kazuo Kuo, Tei-Wei HSUEH-I LU TEI-WEI KUO |
公開日期: | 2007 | 期: | asp-dac | 起(迄)頁: | 866-871 | 來源出版物: | Asia and South Pacific Design Automation Conference | 摘要: | Power-aware and energy-efficient designs play important roles for modern hardware and software designs, especially for embedded systems. This paper targets a scheduling problem on a processor with the capability of dynamic voltage scaling (DVS), which could reduce the power consumption by slowing down the processor speed. The objective of the targeting problem is to minimize the average flow time of a set of jobs under a given energy constraint, where the flow time of a job is defined as the interval length between the arrival and the completion of the job. We consider two types of processors, which have a continuous spectrum of the available speeds or have only a finite number of discrete speeds. Two algorithms are given: (1) An algorithm is proposed to derive optimal solutions for processors with a continuous spectrum of the available speeds. (2) A greedy algorithm is designed for the derivation of optimal solutions for processors with a finite number of discrete speeds. The proposed algorithms are extended to cope with jobs with different weights for the minimization of the average weighted flow time. The proposed algorithms are also evaluated with comparisons to schedules which execute jobs at a common effective speed. © 2007 IEEE. |
URI: | http://www.scopus.com/inward/record.url?eid=2-s2.0-46649092327&partnerID=MN8TOARS http://scholars.lib.ntu.edu.tw/handle/123456789/331819 http://ntur.lib.ntu.edu.tw/bitstream/246246/232844/-1/11.pdf |
DOI: | 10.1109/ASPDAC.2007.358098 | SDG/關鍵字: | Algorithms; Boolean functions; Computer aided design; Conservation; Dielectric losses; Digital integrated circuits; Embedded systems; Energy efficiency; Industrial engineering; Integrated circuits; Mechanization; Optimal systems; Software design; Voltage stabilizing circuits; Wireless telecommunication systems; Continuous spectrum; Design automation conference (DAC); Discrete speeds; Dynamic voltage scaling (DVS); energy constraints; Energy-efficient designs; Finite numbers; Flow-time; Greedy algorithms; Hardware and software; Optimal Solutions; Power consumption (CE); Power-aware; Processor speeds; Scheduling problems; South Pacific; Two types; Speed |
顯示於: | 資訊工程學系 |
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