Supporting Lightweight Row Migration for Asymmetric-Subarray DRAM
Date Issued
2014
Date
2014
Author(s)
Lin, Ying-Chen
Abstract
The evolution of DRAM technology has been driven by capacity and bandwidth during the last decade. In contrast, DRAM access latency stays relatively constant and is trending to increase during the same period. Having smaller bitline length in a DRAM device will reduce the device access latency. However by doing so it will impact the array efficiency. In the mainstream market, manufacturers are not willing to trade capacity for latency. Prior works [1, 2] had proposed hybrid-bitline DRAM design to overcome this problem. They hybrid long and short bitline designs on the same chip to form fast and slow levels, and the capacity lost is amortized. However, the main drawbacks of those methods are either intrusive to the circuit design [1], or there’s no direct way to migrate data between the fast and slow level [2]. In this paper, we proposed a novel and low cost way to allow data to migrate between subarrays. Applying this design to asymmetric sub-array DRAM, we proposed a simple management mechanism and explored many management related policies. We showed that with this new design and simple management technique we could achieve 7.25% and 11.77% performance improvement in single- and multi-programming workloads, respectively over a system with traditional homogeneous DRAM. This gain is above 80% of the potential performance gain of a system based on a hypothetical DRAM which is made out of short bitlines entirely.
Subjects
DRAM
Asymmetric Subarray
Data Migration
Type
thesis