https://scholars.lib.ntu.edu.tw/handle/123456789/119981
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor | 邱奕鵬 | en |
dc.contributor | 臺灣大學:光電工程學研究所 | zh_TW |
dc.contributor.author | 吳啟宏 | zh |
dc.contributor.author | Wu, Chi-Huang | en |
dc.creator | 吳啟宏 | zh |
dc.creator | Wu, Chi-Huang | en |
dc.date | 2007 | en |
dc.date.accessioned | 2007-11-25T23:32:57Z | - |
dc.date.accessioned | 2018-07-05T02:43:24Z | - |
dc.date.available | 2007-11-25T23:32:57Z | - |
dc.date.available | 2018-07-05T02:43:24Z | - |
dc.date.issued | 2007 | - |
dc.identifier | zh-TW | en |
dc.identifier.uri | http://ntur.lib.ntu.edu.tw//handle/246246/50753 | - |
dc.description.abstract | 摘要 在本論文中, 我們使用 FPGA 來實現時域有限差分法 (FDTD)。FDTD 具有假設與近似少, 程式化容易,可分析時域變化等許多優點, 是一套功能非常強大的演算法。近來隨著電腦技術進步與奈米元件發展等因素, 在無線及光電領域越來越重要, 不過這方法需要龐大的計算時間與記憶體, 所以利用 FPGA 來縮短FDTD 的運算時間, 首先設計 FPGA 專注在 FDTD 的運算; 並透過時脈分配設計成管線化, 縮短指令的運算時間; 再搭配 Block RAM 雙埠及其高速的特性處理疊代運算的結果及暫存值的部份, 減少 FDTD 處理資料讀取的時間; 最後再加入平行運算到設計中; 綜合以上各項方法可以使速度明顯提升。 本文使用的FPGA是Xilinx的Spartan-3XC3S1500,數值表示方法是遵照IEEE-754 32 bit 的單精確度浮點數的規格, FDTD 的模擬系統是利用 SPI 介面將參數及初始值寫入, 並透過 VGA 介面將 FPGA 的運算結果讀出分析。 結果顯示, 即使在沒有平行處理的情況下, 將 FPGA 設計在 100 MHz 時的工作頻率, 在 1D FDTD 的結果中, 運算速度約是一般 2.01 GHz 個人電腦的30 倍; 在 2D FDTD 的結果大約是 15 倍。 當 FPGA 跟一般個人電腦工作在相同的頻率下, FPGA 的速度是一般個人電腦的數百倍。 最後在 1D FDTD 中加入兩組平行運算處理後,速度大約可以增加為兩倍。 | zh_TW |
dc.description.abstract | In this thesis, we use field programmable gate array (FPGA) to implement finite-difference time-domain (FDTD).FDTD is a very powerful algorithm with advantages of minimum assumption and approximation, easy programming, and ability to analyze time domain variation. It has recently become more and more important in the field of wireless and optoelectronics due to the advancement of computer technology and the development of nanodevices. However, it requires a huge amount of computation time and memory.Thus, we use FPGA to reduce FDTD computation time.First, FPGA is designed to dedicate to FDTD calculation.Second, pipelining is achieved by means of clock arrangement to reduce computation time of instruction.Third, data access time is reduced by handling recursive calculation and temporary value with high-speed dual-port Block RAM.Finally, parallelism is added into design.Combining the strength above, the computation is greatly speeded up. The FPGA used is Xilinx Spartan-3 XC3S1500.The numerical representation complies with the IEEE-754 32 bit single-precision floating-point specification.In the FDTD simulation system, parameters and initial values are written via SPI interface,and the results computed by the FPGA are read out for analysis through the VGA interface. Our results show that the computation speed of 1D FDTD simulation is 30 times faster that of an ordinary 2.01 GHz personal computer when FPGA operated at clock rate of 100 MHz, and 15 times faster for 2D FDTD simulation even without parallelism.Equivalently, it can be hundreds times faster at the same clock rate.Finally, computation speed is doubled approximately by using two parallel computation units for 1D FDTD simulation. | en |
dc.description.tableofcontents | 目錄 1 背景知識 8 1.1 VHDL . . . . . . . . . . . . . . . . . . . . . . . . .. . . 9 1.2 FPGA 簡介 . . . . . . . . . . . . . . . . . . . . . . 10 1.3 數值表示法 . . . . . . . . . . . . . . . . . . . . . .14 1.3.1 定點數 . . . . . . . . . . . . . . . . . . . . 14 1.3.2 浮點數 . . . . . . . . . . . . . . . . . . . . 14 2 有限時域差分法 (FDTD) 的原理 17 2.1 馬克斯威爾方程式 . . . . . . . . . . . . . . . 17 2.2 Yee 的 FDTD . . . . . . . . . . . . . . . . .. . . . 18 2.2.1 二維 FDTD 方法 . . . . . . . . . . . 20 2.3 FDTD計算的要點 . . . . . . . . . . . . .. . . . 22 2.3.1 細胞 寸大小 . . . . . . . . . . . . . . . 22 2.3.2 時間間隔 . . . . . . . . . . . . . . . . . . 22 2.4 FDTD的應用 . . . . . . . . . . . . . . .. . . . . . 23 3 FPGA 發展平台 25 3.1 系統簡介 . . . . . . . . . . . . . . . . . . . . . . . . 25 3.2 Block RAM . . . . . . . . . . . . . . . . . . . . . . . 29 3.3 SPI 介面 . . . . . . . . . . . . . . . . .. . . . . . . . 33 3.4 VGA傳輸介面 . . . . . . . . . . .. . . . . . . . . 34 3.5 ModelSim . . . . . . . . . . . . . . . . . . . . . . . . 35 4 FDTD 設計方法與原理 38 4.1 系統建置 . . . . . . . . . . . . . . . . . . . . . . . 38 4.2 記憶體配置 . . . . . . . . . . . . . . . . . . . . . 39 4.3 設計流程 . . . . . . . . . . . . . . . . . . . . . . . 40 4.4 平行運算 . . . . . . . . . . . . . . . . . . . . . . . 43 5 模擬與系統的實現 54 5.1 1D FDTD 模擬結果 . . . . . . . . . . . . . . . 54 5.1.1 電磁場 . . . . . . . . . . . . . . . . . . . . . . . . 54 5.1.2 點波源 . . . . . . . . . . . . . . . . . . . . . . . . 54 5.2 2D FDTD 模擬結果 . . . . . . . . . . . . . . . 54 5.2.1 電磁場 . . . . . . . . . . . . . . . . . . . . . . . . 55 5.2.2 點波源 . . . . . . . . . . . . . . . . . . . . . . . . 55 5.3 效能比較 . . . . . . . . . . . . . . . . . .. . . . . . 55 5.4 系統實現與驗證 . . . . . . . . . . . .. . . . . . 56 6 結論 69 參考文獻 70 | zh_TW |
dc.format.extent | 9946276 bytes | - |
dc.format.mimetype | application/pdf | - |
dc.language | zh-TW | en |
dc.language.iso | en_US | - |
dc.subject | 可程式化邏輯陣列 | en |
dc.subject | 時域有限差分法 | en |
dc.subject | FPGA | en |
dc.subject | FDTD | en |
dc.subject | BlockRAM | en |
dc.title | 使用可程式化邏輯陣列實現時域有限差分法 | zh |
dc.title | FPGA Implementation of Finite-Difference Time-Domain Algorithm | en |
dc.type | thesis | en |
dc.identifier.uri.fulltext | http://ntur.lib.ntu.edu.tw/bitstream/246246/50753/1/ntu-96-J94941006-1.pdf | - |
dc.relation.reference | [1] A. Taflove and S. C. Hagness, Computational Electrodynamics: The Finite-Di?erence Time-Domain Method, 3rd ed., Boston: Artech House, 2005. [2] K. S. Kunz and R. J. Luebbers, The Finite Di?erence Time Domain Method for Electromagnetics, CRC Press, 1993. [3] S.E.Krakiwsky, L.E. Turner, and M.M. Okoniewski, “Acceleration of finite-di?erence time-domain (FDTD) using graphics processor units (GPU),” IEEE, MIT-S Digest Vol.2, pp.1033-1036, 2004. [4] C. He, W. Zhao, and Mi Lu, “FPGA-based high-order finite diference algorithm for 2D acoustic wave propagation problems,” European regional science association (ERSA), 2005. [5] C. He, W. Zhao, and Mi Lu, “Time domain numerical simulation for transient wave equations on reconfigurable coprocessor platform,”13th, Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), 2005. [6] http://www.cic.org.tw. [7] Xilinx,Inc.,http://www.xilinx.com. [8] W. Chen, P. Kosmas, M. Leeser, and C. Rappaport, “An FPGA implementation of the two dimensional finite-difference dime-domain(FDTD) algorithm,” 12th, ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), 2004 [9] R. N. Schneider, L. E. Turner and M. M. Okoniewski, “Application of FPGA Technology to Accelerate the finite-difference time-domain (FDTD) Method,” presented at the Tenth ACM International Symposium on Field-Programmable Gate Arrays (FPGA),Monterey, CA, 2002. [10] F. E. Ortiz, J. R. Humphrey, J. P. Durbano, and D. W. Prather, ”A study on the design of floating-point functions in FPGAs,” International Conference on Field Programmable Logic and Applications (FPL), vol. 2778, pp. 1131-1134, 2003. [11] F. E. Ortiz, ”Design of FPGA-oriented floating-point adders and multipliersinVHDL,”UniversityofDelaware, Newark, M.E.E.The-sis, 2003. [12] IEEE Standards, ANSI/IEEE Standard 754-1985, Standard for binary floating point arithmetic [13] K. S. Yee, “Numerical solution of initial boundary value problems involving Maxwell’s equations in isotropic media,” IEEE Trans. Antennas Propagat., vol. 14, pp. 302-307, 1966. [14] J. P. Durbano, F. E. Ortiz, J. R. Humphrey, P. F. Curt, and D. W.Prather, “Hardware acceleration of the 3D finite-difference time-domain method,” IEEE AP-S International Symposium on Antennas and Propagation, 2004 [15] S. Hauck, “The roles of FPGAs in reprogrammable systems,” Proceedings of the IEEE, Vol.86, No.4, pp.615-639, 1998. [16] http://zeppelinx.com/index.htm. [17] http://www.mentorg.com.tw. [18] S. Matsuoka and H. Kawaguchi, “ FPGA implementation of the FDTD data flow machine,” IEEE, Wireless Communication Tech. Topical Conf. pp.418-419, 2003. [19] J. P. Durbano, F. E. Ortiz, J. R. Humphrey, P. F. Curt, and D. W.Prather, “FPGA-based acceleration of the 3D finite-difference time-domain method,” Proc. 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), 2004. [20] L. Verducci, P. Placidi, P. Ciampolini, A. Scorzoni, and L. Roselli,”A standard cell hardware implementation for finite-difference time-domain (FDTD) calculation,” IEEE MTT-S International, Vol.3,pp.2085- 2088 , 2003. [21] J. P. Durbano, F. E. Ortiz, J. R. Humphrey, D. W. Prather, and M. S. Mirotznik, “Hardware implementation of a three-dimensional finite-difference time-domain algorithm,” IEEE Antennas and Wireless Prop agation Letters, 2003. [22] H. Suzuki, Y. Takagi, R. Yamaguchi and S. Uebayashi, “FPGA implementation of FDTD algorithm ,” IEEE, Microwave Conf. Proc.APMC. Vol.5, pp.1-4, 2005. [23] 胡振華, VHDL 與FPGA 設計, 初版, 全華, 2001. [24] 鄭群星,FPGA/CPLD 數位晶片設計入門-使用 Xilinx ISE 發展系統, 二版, 全華, 2006. [25] J. J. Labrosse, 嵌入式系統構件, 全華, 2005. [26] 林振華, 電磁場與天線分析使用時域有限差分法 (FDTD), 全華,1999. [27] 林容益, FPGA 數位 IC 電路設計與應用及實務, 全華, 2006. [28] 邱奕鵬、 吳啟宏及綦凱宏, “以硬體實現時域有限差分的光電元件模擬,”國科會計畫 NSC 95-2221-E-002-285, 2006. | zh_TW |
item.openairecristype | http://purl.org/coar/resource_type/c_46ec | - |
item.openairetype | thesis | - |
item.languageiso639-1 | en_US | - |
item.grantfulltext | open | - |
item.cerifentitytype | Publications | - |
item.fulltext | with fulltext | - |
顯示於: | 光電工程學研究所 |
檔案 | 描述 | 大小 | 格式 | |
---|---|---|---|---|
ntu-96-J94941006-1.pdf | 23.31 kB | Adobe PDF | 檢視/開啟 |
在 IR 系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。