射頻週邊掃描技術
Date Issued
2003-10-31
Date
2003-10-31
Author(s)
DOI
912218E002035
Abstract
This project is developing the RF boundary scan technology. Boundary scan (IEEE 1149.1) is a
popular testing method for digital systems to increase the system testability and lower the testing cost.
This project will extend the coverage of boundary scan from digital circuits to RF circuits (like, 5GHz
WLAN). Currently, there are many new boundary scan standards (IEEE 1149.4/1149.6), which intend
to extend the boundary scan coverage to analog circuits (< 1 MHz) or high speed digital circuits.
Nevertheless, these new standards cannot cover the demand of RF circuit test for System-On-Chip
(SOC) ICs (like 2.4 GHz Bluetooth technology). One of the boundary scan bottlenecks for RF circuits
is the loading effect from Boundary Scan Cell (BSC) to RF circuits. Adding the low-frequency BSC to
the input/output terminals of RF circuits will degrade the RF performance. If the loading effect can be
minimized, then the RF input/output can be included into the coverage of boundary scan.
The first task in this project is to simulate the isolation between the RF signals and the BSC,
which is to minimize the loading effects during the normal RF operations, and to support normal
boundary scan activities during IEEE 1149.1 test mode. The second task is to utilize CIC’s CMOS
process to design 5 GHz low-noise amplifier (LNA) with BSC and isolation circuits at input. The
performance degradation of LNA with BSC will be discussed. On the other hand, from the RF
designer’s point-of-view, with and without BSC loading effects, the adjustments of RF circuit design
to keep the original RF performance will be studied in this project. This research result will be
published in IEEE 2004 VLSI Test Symposium.
Subjects
RF Boundary Scan
RFIC
RF-SOC
SOC Testing
Publisher
臺北市：國立臺灣大學電信工程學研究所
Type
report
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