射頻週邊掃描技術

Abstract

本計畫開發射頻週邊掃描技術，週邊掃描（IEEE 1149.1）已廣泛使用於數位系統中，可大 幅提昇整個系統的可測試性，以及降低測試的成本，本計畫將擴大週邊掃描的涵蓋範圍由數位 電路擴展至射頻電路（如5 GHz WLAN），目前有許多新的週邊掃描測試標準的開發（IEEE 1149.4/1149.6），都希望能擴展週邊掃描至類比電路（<1 MHz）或高速數位電路，但這些新的 測試標準仍未能涵蓋系統晶片（SOC）中射頻（RF）電路的測試需求（如2.4 GHz 藍芽技 術）。其中技術的瓶頸在於週邊掃描電路對於射頻電路的負載效應過大，當週邊掃描的低頻數 位電路加入射頻輸出（入）端時，此負載效應使射頻設計不易保持原本的射頻性能，若能減少 此負載效應至最小，那射頻輸出（入）端即可納入週邊掃描的工作範圍。 本計畫首先對隔離射頻信號與週邊掃描負載的方法進行模擬，以便在正常射頻工作下將週 邊掃描對射頻信號的負載減至最小，同時在測試模態（Test mode）下，週邊掃描仍可與其他電 路匹配依照週邊掃描（IEEE 1149.1）標準正常工作，其次，CIC 的CMOS 製程將被使用來設計 5GHz 低雜訊放大器（LNA），並在輸入端加入，隔離電路及週邊掃描電路。在設計中將比較 原本的LNA 的射頻性能，以及加入週邊掃描後對射頻性能的影響。此外，從射頻電路的設計角 度來看，加上週邊掃描的負載對原本的射頻電路設計上要作何種程度的調整，以保持原本的射 頻特性亦為本計畫的探討項目。而此計畫成果將在IEEE2004 VLSI TEST 國際會議發表。

This project is developing the RF boundary scan technology. Boundary scan (IEEE 1149.1) is a popular testing method for digital systems to increase the system testability and lower the testing cost. This project will extend the coverage of boundary scan from digital circuits to RF circuits (like, 5GHz WLAN). Currently, there are many new boundary scan standards (IEEE 1149.4/1149.6), which intend to extend the boundary scan coverage to analog circuits (< 1 MHz) or high speed digital circuits. Nevertheless, these new standards cannot cover the demand of RF circuit test for System-On-Chip (SOC) ICs (like 2.4 GHz Bluetooth technology). One of the boundary scan bottlenecks for RF circuits is the loading effect from Boundary Scan Cell (BSC) to RF circuits. Adding the low-frequency BSC to the input/output terminals of RF circuits will degrade the RF performance. If the loading effect can be minimized, then the RF input/output can be included into the coverage of boundary scan. The first task in this project is to simulate the isolation between the RF signals and the BSC, which is to minimize the loading effects during the normal RF operations, and to support normal boundary scan activities during IEEE 1149.1 test mode. The second task is to utilize CIC’s CMOS process to design 5 GHz low-noise amplifier (LNA) with BSC and isolation circuits at input. The performance degradation of LNA with BSC will be discussed. On the other hand, from the RF designer’s point-of-view, with and without BSC loading effects, the adjustments of RF circuit design to keep the original RF performance will be studied in this project. This research result will be published in IEEE 2004 VLSI Test Symposium.