https://scholars.lib.ntu.edu.tw/handle/123456789/147601
Title: | Analysis of the Gate–Source/Drain Capacitance Behavior of a Narrow-Channel FD SOI NMOS Device Considering the 3-D Fringing Capacitances Using 3-D Simulation | Authors: | Chen, Chien-Chung Kuo, James B. Su, Ke-Wei Liu, Sally |
Keywords: | Capacitance;CMOSFETs;modeling;silicon-oninsulator (SOI) technology, simulation | Issue Date: | Oct-2006 | Publisher: | Taipei:National Taiwan University Dept Elect Engn | Journal Volume: | VOL. 53 | Journal Issue: | NO. 10 | Start page/Pages: | - | Source: | IEEE Transactions on Electron Devices | Abstract: | This paper reports an analysis of the gate–source/ drain capacitance behavior of a narrow-channel fully depleted (FD) silicon-on-insulator (SOI) NMOS device considering the three-dimensional (3-D) fringing capacitances. Based on the 3-D simulation results, when the width of the FD SOI NMOS device is scaled down to 0.05 μm, the inner-sidewall-oxide fringing capacitance (CFIS), due to the fringing electric field at the edge of the mesa-isolated structure of the FD SOI NMOS device biased at VG = 0.3 V and VD = 1 V, is the second largest contributor to the gate–source capacitance (CGS). Thus, when using nanometer CMOS devices with a channel width smaller than 0.1 μm, CFIS cannot be overlooked for modeling gate–source/drain capacitance (CGS/CGD). |
URI: | http://ntur.lib.ntu.edu.tw//handle/246246/200611150121241 | Other Identifiers: | 246246/200611150121241 |
Appears in Collections: | 電機工程學系 |
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