https://scholars.lib.ntu.edu.tw/handle/123456789/148594
標題: | A simple and efficient deadlock recovery scheme for wormhole routed 2-dimensional meshes | 作者: | Wang, Shih-Chang Lin, Hung-Yau Kuo, Sy-Yen Huang, Yennun |
公開日期: | 十二月-1999 | 起(迄)頁: | - | 來源出版物: | Pacific Rim International Symposium o Dependable Computing, 1999 | 摘要: | In order to avoid deadlocks, prevention-based routing algorithms impose certain routing restrictions which lead to high hardware complexity or low adaptability. If deadlock occurrences are extremely rare, recovery-based routing algorithms become more attractive with respect to hardware complexity and routing adaptability. A simple architecture where each router is provided with an additional special flit buffer was developed to achieving deadlock recovery. Disha-SEQ and Disha-CON are two deadlock recovery schemes based on such an architecture to accomplish sequential recovery and concurrent recovery, respectively. In this paper, we propose a simple recovery scheme for a 2D mesh with the same router architecture, and reduce drawbacks in Disha-SEQ or Disha-CON, such as hardwired tokens, finding the Hamiltonian cycle, Hamiltonian path labeling for each node, and non-minimal path routing. Moreover, the simulation results show that the proposed scheme has a similar performance to Disha-CON and is better than Disha-SEQ. © 1999 IEEE. |
URI: | http://ntur.lib.ntu.edu.tw//handle/246246/2007041910021593 https://www.scopus.com/inward/record.uri?eid=2-s2.0-0010117075&doi=10.1109%2fPRDC.1999.816231&partnerID=40&md5=ffe595daa30f9516c1f2c1e5e20ec90a |
其他識別: | N/A | DOI: | 10.1109/PRDC.1999.816231 | SDG/關鍵字: | Computer architecture; Hamiltonians; Hardware; Network architecture; 2d meshes; Deadlock recovery; Hamiltonian cycle; Hamiltonian path; Hardware complexity; Minimal path; Recovery scheme; Router architecture; Recovery |
顯示於: | 電機工程學系 |
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