https://scholars.lib.ntu.edu.tw/handle/123456789/150120
標題: | Design and implementation of JPEG encoder IP core | 作者: | Lian, Chung-Jr LIANG-GEE CHEN Chang, Hao-Chieh Chang, Yung-Chi |
關鍵字: | Delay; Digital cameras; Discrete cosine transforms; Hardware; Image coding; Image storage; Quantization; Read-write memory; System-on-a-chip; Testing | 公開日期: | 二月-2001 | 卷: | 2001-January | 起(迄)頁: | 29-30 | 來源出版物: | Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC | 會議論文: | Asia and South Pacific Design Automation Conference 2001, ASP-DAC 2001 | 摘要: | A complete, low cost baseline JPEG encoder soft IP and its chip implementation are presented in this paper. It features user-defined, run-time reconfigurable quantization tables, highly modularized and fully pipelined architecture. A prototype, synthesized with COMPASS cell library, has been implemented in TSMC 0.6-μm single-poly triple-metal process. It can run up to 40 MHz at 3.3 V. This IP can be easily integrated into various application systems, such as scanner, PC camera and color FAX, etc. © 2001 IEEE. |
URI: | http://ntur.lib.ntu.edu.tw//handle/246246/2007041910021264 https://www.scopus.com/inward/record.uri?eid=2-s2.0-33646909277&doi=10.1109%2fASPDAC.2001.913273&partnerID=40&md5=90a1d14e97f70faf93867d1f8fb04227 |
其他識別: | N/A | DOI: | 10.1145/370155.370246 10.1109/ASPDAC.2001.913273 |
SDG/關鍵字: | Application specific integrated circuits; Computer aided design; Computer hardware; Cosine transforms; Digital cameras; Discrete cosine transforms; Image coding; Integrated circuit design; Optical image storage; Reconfigurable architectures; System-on-chip; Testing; Chip implementation; Delay; Design and implementations; Fully pipelined architecture; Quantization; Quantization tables; Run-time reconfigurable; System on a chip; Digital image storage |
顯示於: | 電機工程學系 |
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