https://scholars.lib.ntu.edu.tw/handle/123456789/150509
標題: | 5 V, 8 bit, 100 MS/s fully differential CMOS sample-and-hold amplifier | 作者: | Chen, Chun-Chieh Tsao, Hen-Wai |
關鍵字: | Amplifiers; CMOS integrated circuits; Sample and hold circuits | 公開日期: | 二月-1996 | 起(迄)頁: | - | 來源出版物: | Electronics Letters | 摘要: | A 5V, 100MS/s fully differential CMOS sample-and-hold amplifier (SHA) with 8bit accuracy is proposed. Based on the stability limitations of closed-loop SHAs studied in a previous Letter (1995), the proposed SHA is implemented by an open-loop structure using the 'gain-enhanced unity-gain amplifier' to avoid the stability problem and achieve higher operation speed. Simulation results which agree well with experimental results have been obtained to demonstrate the accuracy of the proposed circuit. |
URI: | https://www.scopus.com/inward/record.uri?eid=2-s2.0-0030084449&doi=10.1049%2fel%3a19960234&partnerID=40&md5=77e936ddee9291ba72b2d30bebf469d0 | ISSN: | N/A | 其他識別: | 0013-5194 | DOI: | 10.1049/el:19960234 | SDG/關鍵字: | Amplifiers (electronic); Aspect ratio; Computer simulation; Electric waveforms; Mathematical techniques; Multiplying circuits; Signal theory; Signal to noise ratio; Transconductance; Bias voltage; Closed loop structure; Data acquisition system; Differential mode gain; Gain enhancing factor; Microphotograph; Sample and hold circuits; CMOS integrated circuits |
顯示於: | 電機工程學系 |
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00490922.pdf | 285.5 kB | Adobe PDF | 檢視/開啟 |
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