超大型?米積體電?無格線式全晶片繞線系統 (1/3) Gridless Full-Chip Routing for Very-Large Scale Nanometer ICs

The multilevel routing framework has attracted much
attention recently due to its excellent scalability to handle
very large-scale circuit designs. Most existing multilevel
routers are based on the gridded model and consider only
routability and performance. (For example, our work [21]
presents a multilevel gridded-based router, called MR,
which obtains the highest routability in the literature, based
on a set of commonly used benchmark circuits---The work
was nominated Best Paper at ICCAD-2002.) However, the
grid-based model is not effective to handle many nanometer
electrical effects suchas signal integrity (e.g., crosstalk),
reliability (e.g., antenna effects, metal electromigration),
manufacturability (e.g., optical proximity correction, phase
shift mask, metal filling), for which more sophisticated
geometrical patterns such as variable wire widths and
variable wire spacing are needed for design optimization. In
this three-year project, we intend to (1) model those
important nanometer electrical effects, (2) derive
optimization schemes for them, and (3) develop a signal
integrity-, reliability-, and manufacturability-aware
multilevel, gridless full-chip routing system for very
large-scale nanometer IC designs.