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  4. Quantum Boolean circuit construction and layout under locality constraint
 
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Quantum Boolean circuit construction and layout under locality constraint

Resource
Nanotechnology, 2001. IEEE-NANO 2001. Proceedings of the 2001 1st IEEE Conference on
Journal
1st IEEE Conference on Nanotechnology, IEEE-NANO 2001
Pages
-
Date Issued
2001-10
Date
2001-10
Author(s)
Tsai, I-Ming
Kuo, Sy-Yen  
DOI
10.1109/NANO.2001.966403
DOI
N/A
URI
http://ntur.lib.ntu.edu.tw//handle/246246/2007041910021343
https://www.scopus.com/inward/record.uri?eid=2-s2.0-57649145355&doi=10.1109%2fNANO.2001.966403&partnerID=40&md5=f784cffe7504baa4cdd143937d0209ee
Abstract
The discovery of Shor's prime factorization and Grover's fast database search algorithm have made quantum computing the most rapidly expanding research field recently. Nanotechnology, in particular silicon-based nanoscale device, has been proposed as one of the candidates that can be used to implement a quantum computer. In this paper, we have derived a systematic procedure to realize any general m-to-n bit combinational boolean logic using elementary quantum gates. The quantum circuit layout under the locality constraint is then formulated, together with the gate count evaluation function, to reduce the total number of quantum gates required to implement the circuit. © 2001 IEEE.
Other Subjects
Algorithms; Computation theory; Logic circuits; Logic gates; Quantum computers; Quantum electronics; Quantum optics; Quantum theory; Search engines; Database search algorithms; Evaluation function; Nanoscale device; Prime factorization; Quantum Boolean circuits; Quantum circuit; Quantum Computing; Research fields; Nanotechnology
Type
conference paper
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