https://scholars.lib.ntu.edu.tw/handle/123456789/154729
標題: | Simultaneous Buffer-sizing and Wire-sizing for Clock Trees Based on Lagrangian Relaxation | 作者: | LEE, YU-MIN CHEN, CHARLIE CHUNG-PING YAO-WEN CHANG CHUNG-PING CHEN |
關鍵字: | Buffer-sizing; Clock trees; Interconnect optimization; Lagrangian relaxation; VLSI CAD; Wire-sizing | 公開日期: | 2002 | 卷: | 15 | 期: | 3 | 起(迄)頁: | 587-594 | 來源出版物: | VLSI Design | 摘要: | Delay, power, skew, area and sensitivity are the most important concerns in current clock-tree design. We present in this paper an algorithm for simultaneously optimizing the above objectives by sizing wires and buffers in clock trees. Our algorithm, based on Lagrangian relaxation method, can optimally minimize delay, power and area simultaneously with very low skew and sensitivity. With linear storage overall and linear runtime per iteration, our algorithm is extremely economical, fast and accurate; for example, our algorithm can solve a 6201-wire-segment clock-tree problem using about 1-minute runtime and 1.3-MB memory and still achieve pico-second precision on an IBM RS/6000 workstation. |
URI: | http://www.scopus.com/inward/record.url?eid=2-s2.0-0036454324&partnerID=MN8TOARS http://scholars.lib.ntu.edu.tw/handle/123456789/298314 http://ntur.lib.ntu.edu.tw/bitstream/246246/141371/1/12.pdf |
ISSN: | 1065514X | DOI: | 10.1080/1065514021000012200 | SDG/關鍵字: | Algorithms; Application specific integrated circuits; Computer aided design; Computer simulation; Electric power supplies to apparatus; Integrated circuit layout; Interconnection networks; Iterative methods; Lagrange multipliers; Optimization; Bufer sizing; Clock trees; Interconnect optimization; Lagrangian relaxation; Wire sizing; VLSI circuits |
顯示於: | 電機工程學系 |
在 IR 系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。