https://scholars.lib.ntu.edu.tw/handle/123456789/154735
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Wu, Guang-Ming | en |
dc.contributor.author | Chao, Mango Chia-Tso | en |
dc.contributor.author | YAO-WEN CHANG | en |
dc.creator | Wu G.-M;Chao M.C.-T;Chang Y.-W. | - |
dc.date | 2004 | en |
dc.date.accessioned | 2009-02-25T06:57:26Z | - |
dc.date.accessioned | 2018-07-06T15:26:53Z | - |
dc.date.available | 2009-02-25T06:57:26Z | - |
dc.date.available | 2018-07-06T15:26:53Z | - |
dc.date.issued | 2004 | - |
dc.identifier.issn | 01679260 | - |
dc.identifier.uri | http://www.scopus.com/inward/record.url?eid=2-s2.0-9644276833&partnerID=MN8TOARS | - |
dc.identifier.uri | http://scholars.lib.ntu.edu.tw/handle/123456789/309301 | - |
dc.identifier.uri | http://ntur.lib.ntu.edu.tw//handle/246246/141381 | - |
dc.description.abstract | Improving logic density by time-sharing, time-multiplexed FPGAs (TMFPGAs) have become an important research topic for reconfigurable computing. Due to the precedence and capacity constraints in TMFPGAs, the clustering and partitioning problems for TMFPGAs are different from the traditional ones. In this paper, we propose a two-phase hierarchical approach to solve the partitioning problem for TMFPGAs. With the precedence and capacity considerations for both phases, the first phase clusters nodes to reduce the problem size, and the second phase applies a probability-based iterative-improvement approach to minimize cut cost. Experimental results based on the Xilinx TMFPGA architecture show that our algorithm significantly outperforms previous works. © 2004 Elsevier B.V. All rights reserved. | - |
dc.format | application/pdf | en |
dc.format.extent | 413913 bytes | - |
dc.format.mimetype | application/pdf | - |
dc.language | en | en |
dc.language.iso | en_US | - |
dc.relation | Integration, the VLSI Journal 38 (2): 245-265 | en |
dc.relation.ispartof | Integration | en_US |
dc.subject | Layout; Partitioning; Physical_design | - |
dc.subject.other | Algorithms; Combinatorial circuits; Heuristic methods; Problem solving; Scheduling; Static random access storage; Configurable logic blocks (CLB); Layout; Partitioning; Time-sharing; Field programmable gate arrays | - |
dc.title | A clustering- and probability-based approach for time-multiplexed FPGA partitioning | en |
dc.type | journal article | en |
dc.identifier.doi | 10.1016/j.vlsi.2004.06.003 | - |
dc.identifier.scopus | 2-s2.0-9644276833 | - |
dc.identifier.isi | WOS:000225661300005 | - |
item.fulltext | with fulltext | - |
item.grantfulltext | open | - |
dc.relation.pages | 246-265 | - |
dc.relation.journalvolume | 38 | - |
dc.relation.journalissue | 2 | - |
dc.identifier.uri.fulltext | http://ntur.lib.ntu.edu.tw/bitstream/246246/141381/1/18.pdf | - |
item.openairetype | journal article | - |
item.fulltext | with fulltext | - |
item.openairecristype | http://purl.org/coar/resource_type/c_6501 | - |
item.grantfulltext | open | - |
item.languageiso639-1 | en_US | - |
item.cerifentitytype | Publications | - |
crisitem.author.dept | Electronics Engineering | - |
crisitem.author.dept | Electrical Engineering | - |
crisitem.author.dept | Computer Science and Information Engineering | - |
crisitem.author.dept | Center for Information and Electronics Technologies | - |
crisitem.author.dept | MediaTek-NTU Research Center | - |
crisitem.author.orcid | 0000-0002-0564-5719 | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | Others: University-Level Research Centers | - |
crisitem.author.parentorg | Others: University-Level Research Centers | - |
顯示於: | 電機工程學系 |
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