https://scholars.lib.ntu.edu.tw/handle/123456789/154807
Title: | Memory efficient JPEG 2000 architecture with stripe pipeline scheduling | Authors: | Fang, Hung-Chi Chang, Yu-Wei Cheng, Chih-Chi LIANG-GEE CHEN |
Keywords: | Discrete wavelet transform; Embedded block coding with optimized truncation; Image coding; JPEG 2000 | Issue Date: | 2006 | Journal Volume: | 54 | Journal Issue: | 12 | Start page/Pages: | 4807-4816 | Source: | IEEE Transactions on Signal Processing | Abstract: | Memory issues pose the most critical problem in designing a high-performance JPEG 2000 architecture. The tile memory occupies more than 50% area in conventional JPEG 2000 designs. To solve this problem, we propose a stripe pipeline scheduling. It well matches the throughputs and dataflows of the discrete wavelet transform and the embedded block coding to minimize the data lifetime between the two modules. As a result of the scheduling, the overall memory requirements of the proposed architecture can be reduced to only 8.5% compared with conventional architectures. This effectively reduces the hardware cost of the entire system by more than 45%. Besides reducing the cost, we also propose a two-symbol arithmetic encoder architecture to increase the throughput. By use of this technique, the proposed architecture can achieve 124 MS/s at 124 MHz, which is the highest specification in the literature. Therefore, the proposed architecture is not only low cost but also high speed. © 2006 IEEE. |
URI: | http://ntur.lib.ntu.edu.tw//handle/246246/141469 https://www.scopus.com/inward/record.uri?eid=2-s2.0-33947106862&doi=10.1109%2fTSP.2006.881218&partnerID=40&md5=cfe2aa1e787fa4576e6ba4b33f836c26 |
ISSN: | 1053587X | DOI: | 10.1109/TSP.2006.881218 | SDG/Keyword: | Embedded block coding; Embedded blocks; Optimized truncation; Data flow analysis; Discrete wavelet transforms; Image coding; Logic design; Problem solving; Scheduling; Computer architecture |
Appears in Collections: | 電機工程學系 |
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