https://scholars.lib.ntu.edu.tw/handle/123456789/154807
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Fang, Hung-Chi | en_US |
dc.contributor.author | Chang, Yu-Wei | en_US |
dc.contributor.author | Cheng, Chih-Chi | en_US |
dc.contributor.author | LIANG-GEE CHEN | en_US |
dc.creator | Fang, Hung-Chi; Chang, Yu-Wei; Cheng, Chih-Chi; Chen, Liang-Gee | en |
dc.date | 2006 | en |
dc.date.accessioned | 2009-02-25T09:01:41Z | - |
dc.date.accessioned | 2018-07-06T15:30:02Z | - |
dc.date.available | 2009-02-25T09:01:41Z | - |
dc.date.available | 2018-07-06T15:30:02Z | - |
dc.date.issued | 2006 | - |
dc.identifier.issn | 1053587X | - |
dc.identifier.uri | http://ntur.lib.ntu.edu.tw//handle/246246/141469 | - |
dc.identifier.uri | https://www.scopus.com/inward/record.uri?eid=2-s2.0-33947106862&doi=10.1109%2fTSP.2006.881218&partnerID=40&md5=cfe2aa1e787fa4576e6ba4b33f836c26 | - |
dc.description.abstract | Memory issues pose the most critical problem in designing a high-performance JPEG 2000 architecture. The tile memory occupies more than 50% area in conventional JPEG 2000 designs. To solve this problem, we propose a stripe pipeline scheduling. It well matches the throughputs and dataflows of the discrete wavelet transform and the embedded block coding to minimize the data lifetime between the two modules. As a result of the scheduling, the overall memory requirements of the proposed architecture can be reduced to only 8.5% compared with conventional architectures. This effectively reduces the hardware cost of the entire system by more than 45%. Besides reducing the cost, we also propose a two-symbol arithmetic encoder architecture to increase the throughput. By use of this technique, the proposed architecture can achieve 124 MS/s at 124 MHz, which is the highest specification in the literature. Therefore, the proposed architecture is not only low cost but also high speed. © 2006 IEEE. | - |
dc.format | application/pdf | en |
dc.format.extent | 1822795 bytes | - |
dc.format.mimetype | application/pdf | - |
dc.language | en | en |
dc.language.iso | en_US | - |
dc.relation.ispartof | IEEE Transactions on Signal Processing | - |
dc.subject | Discrete wavelet transform; Embedded block coding with optimized truncation; Image coding; JPEG 2000 | - |
dc.subject.other | Embedded block coding; Embedded blocks; Optimized truncation; Data flow analysis; Discrete wavelet transforms; Image coding; Logic design; Problem solving; Scheduling; Computer architecture | - |
dc.title | Memory efficient JPEG 2000 architecture with stripe pipeline scheduling | en |
dc.type | journal article | en |
dc.identifier.doi | 10.1109/TSP.2006.881218 | - |
dc.identifier.scopus | 2-s2.0-33947106862 | - |
dc.relation.pages | 4807-4816 | - |
dc.relation.journalvolume | 54 | - |
dc.relation.journalissue | 12 | - |
dc.identifier.uri.fulltext | http://ntur.lib.ntu.edu.tw/bitstream/246246/141469/1/57.pdf | - |
item.openairecristype | http://purl.org/coar/resource_type/c_6501 | - |
item.openairetype | journal article | - |
item.languageiso639-1 | en_US | - |
item.grantfulltext | open | - |
item.cerifentitytype | Publications | - |
item.fulltext | with fulltext | - |
crisitem.author.dept | Electrical Engineering | - |
crisitem.author.dept | Electronics Engineering | - |
crisitem.author.dept | Networking and Multimedia | - |
crisitem.author.orcid | 0000-0001-9746-9355 | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
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