https://scholars.lib.ntu.edu.tw/handle/123456789/173735
標題: | A 50-Gb/s 10-mW analog equalizer using transformer feedback technique in 65-nm CMOS technology | 作者: | Lu, Jian-Hao SHEN-IUAN LIU |
關鍵字: | CMOS; Equalizer; Transformer feedback | 公開日期: | 2009 | 卷: | 56 | 期: | 10 | 起(迄)頁: | 783-787 | 來源出版物: | IEEE Transactions on Circuits and Systems II: Express Briefs | 摘要: | A 50-Gb/s low-power analog equalizer has been realized in 65-nm CMOS technology. This equalizer adopts the proposed transformer feedback technique to achieve a peaking gain of 18 dB at 25 GHz and low-power dissipation. The whole equalizer without the output buffer consumes 10 mW from a 1-V supply. The chip occupies 0.35 × 0.27 mm2. For a 50-Gb/s pseudorandom bit sequence of 27 - 1, the measured bit error rate is less than 10-12, and the measured maximum root-mean-square and peak-to-peak jitters are 2.7 and 12.4 ps, respectively. © 2009 IEEE. |
URI: | http://scholars.lib.ntu.edu.tw/handle/123456789/352073 http://ntur.lib.ntu.edu.tw/bitstream/246246/237193/-1/07.pdf |
ISSN: | 15497747 | DOI: | 10.1109/TCSII.2009.2030536 | SDG/關鍵字: | Bit error rate; CMOS integrated circuits; Feedback; Analog equalizers; CMOS technology; Low-power dissipation; Output Buffer; Peak-to-peak; Pseudo random bit sequences; Root Mean Square; Transformer feedback; Equalizers |
顯示於: | 電子工程學研究所 |
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