前瞻矽鍺/高介電質/金屬閘極元件及模組技術 –總 計劃(I)

Abstract

本整合型總計畫將以high k、SiGe及 metal gate(子計畫三與子計畫四)三項模組 技術為主，模擬並設計新型元件、 MOS 電子元件及光電元件(子計畫一)，因為要增 加 CMOS的附加價值，如光電元件及記憶 體元件可擴大CMOS的應用市場，是需要 學校發展創意與理論分析的好題目，而 CMOS元件本身的scaling，在本計畫則是在 理論分析與模擬(子計畫一)，與模組驗證 (子計畫三與四)上來進行研究 。本計畫研 究SiGe、high k、metal gate 三項技術並加 以整合成模組技術。 各子計畫的摘要如下。 子計畫一： 蒙地卡羅模擬軟體ISE-SPARTATM 來 模擬分析在應變矽N 型及P 型金氧半場效 電晶體中，當有效通道長度漸次縮短至 10nm 時，因應變而造成之效能提升的情 形。當應變矽/鬆弛矽鍺結構之N 型及P 型 金氧半場效電晶體在其矽鍺基板之鍺濃度 為40%，且有效通道長度僅剩10nm 時， 所得到之驅動電流增益仍能個別維持在 25%與17%。 研究以矽鍺為中心體的應變矽新型鰭 形三閘場效電晶體其電特性。發現由於應 變矽通道的遷移率增加與異質接面的侷限 電子效果，使其在NMOS 的subthreshold 上有不錯的改善。而PMOS 則因異質接面 對電洞會形成埋層通道效應，所以改善情 況不是很好，但使用漸變矽鍺界面後，其 情況以大幅改善。 研究MOS 結構之Ge/Si QDIPs 在長波 長偵測器應用上3-10μm 的特性，並利用 K.P 理論計算由wetting layer 造成之矽/ 鍺價電帶結構的次能帶，與可能之吸收頻 譜躍遷，並與實驗之PL 比較，驗證3-10μm 的響應來自於wetting layer。 子計畫三： 由於半導體工業之製程技術快速發 展，過去以尺寸微縮的方式，藉由元件個 數的提升來增加其傳輸之速度。然而發展 至今，傳統以矽(Si)為基底之元件，因受到 本身基底材料特性之限制，若欲持續在使 元件之尺寸向下微縮，將造成許多製程上 之影響。因此，我們尋求以碳和矽之間所 形成的異質接面及利用其晶格不匹配等特 性所成長出的應變碳化矽/矽基板當成新的 基底材料，以延續摩爾定律模式並持續發 展新世代的微電子技術。子計畫三主要的 研究了(1)應變碳化矽當基板製作之二氧化 鉿薄膜電容器的製程開發。(2)高介電係數材 料應用在碳化矽基板之漏電流機制分析能 力建立。 子計畫四： 光電產業被認為是下一個具有發展潛 力的明星產業。目前全球光電元件的產值 約佔整個半導體產業的6 % (10 B 美金)，並且其比重會隨著時間繼續增加。以2002 年為例，台灣光電產業產值即高達3000 億 新台幣，其中光電顯示器及光儲存產品佔 大多數，而光通訊用元件及發光、光偵測 元件則相對較少。而在這些光電產品中， 矽基元件多用在CMOS image sensor（數位 照相用），liquid crystal on Si（顯示器用）， 及array waveguide grating(光通訊用)上。因 此若是能利用CMOS 產業所發展的技術 來製造光電元件，增加矽的功能（有人稱 為“silicon+” ） ， 即是研究CMOS optoelectronics的目的。本研究即希望能利 用先進的矽鍺、high k 及metal gate 技術並 結合其他子計畫來製成新型量子光電元件 及高頻光通訊用零組件。

The main project covers three module technologies, including high K, SiGe and metal gate (subproject 3 & 4), and four device technologies including simulation and modeling of nano-scaled electronic and optoelectronic devices ( subproject1), MOS electronic device (subproject 3), and CMOS optoelectronics (subproject 4). Based on the concept that “It will be CMOS, if CMOS can do,” we try to extend the CMOS kingdom to new applications using CMOS-based new technologies. In this main project, SiGe, high k, and metal gate technologies have been investigated and integrated in the modulus technology. The abstracts of subprojects are scheduled as following. Subproject 1: A commercial Monte Carlo simulator ISE-SPARTATM was used to simulate the strain-induced performance enhancement in N- and P-type strained Si MOSFETs with Leff scaling down to 10nm. When the effective gate length of N- and P-type MOSFETs with Ge content of 40% in SiGe substrate are close to 10nm, the on-current still has 25% and 17% enhancement, respectively. Strained Si surrounding the SiGe embedded body on a SOI (silicon on insulator) substrate forms a novel Tri-gate FET. This novel device with the enhanced carrier mobility and heterojunction confinement is demonstrated with greatly improved performance for NMOS by 3-D simulation. The PMOS is not improved as much as NMOS due to the buried channel at the Si/SiGe abrupt heterojunction. Using grade-back layer among strained Si and relaxed SiGe body can significantly improve the performance of PMOS. The MOS Ge/Si QDIPs for 2~10μm are successfully demonstrated. Since the Ge wetting layer could be seem as simply quantum well structure, the valance band bound state energy is calculated by k‧p method. By calculating the total intersubband transitions, a absorption peak is located at 7.5μm. From PL spectrum and the theoretical calculation results, the quantum dot structure is responsible for 2~3μm response with high operation temperature and the wetting layer structure (quantum well) is responsible for 3~10μm response. Subproject 3: A high-quality ultra thin HfO2/Hf silicate film is deposited on tensile-strained-SiC alloy layers using the HfO2/Hf gate stack technique. The electrical characteristics of Pt/Hf-silicate/SiC/p-Si/Al structures are similar to those of Pt/Hf-silicate/p-Si/Al structures. The significant improvements in the electrical characteristics such as leakage current, effective dielectric constant, interface state density and fixed oxide charge density are observed for HfO2/Hf gate stacks as compared with HfO2 films on SiC alloy layers. Using this gate stack technique, a high dielectric constant (~15.5) for HfO2/Hf silicate can be obtained, and this technique can be applied to fabricate ultra short SiC surface channel metal oxide semiconductor field effect transistor (MOSFET) devices. Subproject 4: The optoelectronics industry is a star industry with potential. The value of output in optoelectronics devices is about 6 percentages (10 B US dollar) of total semiconductor industry, and it will be increased with time. For example, the value of output in optoelectronics industry in Taiwan is 3000 hundred million, which is almost contributed by display and storage. The optical communication, emitting, optical detection device have few contribution to the value of output in optoelectronics industry. In the past, the COMS image sensor (for digital camera), liquid crystal on Si (for display), and the array waveguide grating (for optical communication) are all Si base device. So that it is the purpose for researching COMS optoelectronics to enhance the function of Si (called “silicon+”) if the optoelectronics device can be made of COMS technology. The combination of advance SiGe, high k, and metal gate for novel quantum optoelectronics device and high frequency optical communication is purpose in this research.