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  4. 前瞻矽鍺/高介電質/金屬閘極元件及模組技術 –總 計劃(I)
 
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前瞻矽鍺/高介電質/金屬閘極元件及模組技術 –總 計劃(I)

Date Issued
2005-07-31
Date
2005-07-31
Author(s)
劉致為  
DOI
932215E002018
URI
http://ntur.lib.ntu.edu.tw//handle/246246/20044
Abstract
The main project covers three module technologies, including high K, SiGe and metal gate (subproject 3 & 4), and four device technologies including simulation and modeling of nano-scaled electronic and optoelectronic devices ( subproject1), MOS electronic device (subproject 3), and CMOS optoelectronics (subproject 4). Based on the concept that “It will be CMOS, if CMOS can do,” we try to extend the CMOS kingdom to new applications using CMOS-based new technologies. In this main project, SiGe, high k, and metal gate technologies have been investigated and integrated in the modulus technology. The abstracts of subprojects are scheduled as following. Subproject 1: A commercial Monte Carlo simulator ISE-SPARTATM was used to simulate the strain-induced performance enhancement in N- and P-type strained Si MOSFETs with Leff scaling down to 10nm. When the effective gate length of N- and P-type MOSFETs with Ge content of 40% in SiGe substrate are close to 10nm, the on-current still has 25% and 17% enhancement, respectively. Strained Si surrounding the SiGe embedded body on a SOI (silicon on insulator) substrate forms a novel Tri-gate FET. This novel device with the enhanced carrier mobility and heterojunction confinement is demonstrated with greatly improved performance for NMOS by 3-D simulation. The PMOS is not improved as much as NMOS due to the buried channel at the Si/SiGe abrupt heterojunction. Using grade-back layer among strained Si and relaxed SiGe body can significantly improve the performance of PMOS. The MOS Ge/Si QDIPs for 2~10μm are successfully demonstrated. Since the Ge wetting layer could be seem as simply quantum well structure, the valance band bound state energy is calculated by k‧p method. By calculating the total intersubband transitions, a absorption peak is located at 7.5μm. From PL spectrum and the theoretical calculation results, the quantum dot structure is responsible for 2~3μm response with high operation temperature and the wetting layer structure (quantum well) is responsible for 3~10μm response. Subproject 3: A high-quality ultra thin HfO2/Hf silicate film is deposited on tensile-strained-SiC alloy layers using the HfO2/Hf gate stack technique. The electrical characteristics of Pt/Hf-silicate/SiC/p-Si/Al structures are similar to those of Pt/Hf-silicate/p-Si/Al structures. The significant improvements in the electrical characteristics such as leakage current, effective dielectric constant, interface state density and fixed oxide charge density are observed for HfO2/Hf gate stacks as compared with HfO2 films on SiC alloy layers. Using this gate stack technique, a high dielectric constant (~15.5) for HfO2/Hf silicate can be obtained, and this technique can be applied to fabricate ultra short SiC surface channel metal oxide semiconductor field effect transistor (MOSFET) devices. Subproject 4: The optoelectronics industry is a star industry with potential. The value of output in optoelectronics devices is about 6 percentages (10 B US dollar) of total semiconductor industry, and it will be increased with time. For example, the value of output in optoelectronics industry in Taiwan is 3000 hundred million, which is almost contributed by display and storage. The optical communication, emitting, optical detection device have few contribution to the value of output in optoelectronics industry. In the past, the COMS image sensor (for digital camera), liquid crystal on Si (for display), and the array waveguide grating (for optical communication) are all Si base device. So that it is the purpose for researching COMS optoelectronics to enhance the function of Si (called “silicon+”) if the optoelectronics device can be made of COMS technology. The combination of advance SiGe, high k, and metal gate for novel quantum optoelectronics device and high frequency optical communication is purpose in this research.
Subjects
SiGe
strain
mobility
Quantum
Dot
SiC
high K
metal gate
Publisher
臺北市:國立臺灣大學電子工程學研究所
Type
report
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